Job Description
QCT DDR PHY team develops high-speed/low-power DRAM memory interface for all Qualcomm chipsets in latest DDR technologies. This position requires involvement in various aspects of DDR system architecture planning, competitive analysis, front-end and physical design, mostly through analysis and guidance of the team on timing considerations from architecture through tapeout. Responsibilities include:Focused analysis and ownership of specific DDR PHY architecture componentsDevelopment of system timing budgets, both on-die and off-chip.Competitive analysis of power/area/performance.Identification and analysis of timing bottlenecks and mitigation solutions.Guidance to front-end and physical teams on all aspects of timing considerations.Development and support of PrimeTime STA timing constraints.Development of scripted automation for efficient data processing.
Responsibilities + Skills
Excellent communication skills and ability to work across multiple teams across global locations.
Education
VLSI circuits understanding, including Spice analysis.2+ years industry experience with static timing analysis (STA) and PrimeTime constraints development.
Experience
