Job Description
As a Physical Design and Timing Engineer, you will be responsible for the physical and electrical design and development of high-frequency microprocessor chips at the chiplet and chip hierarchies. You will use tools to optimize buffering and wiring to meet timing, routability, and power constraints. You will create and manage timing constraints in a hierarchical design setting. You will collaborate with internal EDA team/external tool vendors to develop and optimize tools and methodologies with focus on timing analysis and optimization.Your Role and ResponsibilitiesDesign and develop very high frequency, deep sub-micron CMOS chips. Use sophisticated design tools and leading-edge CMOS technology to implement circuit schematics (custom and ASIC) and verify against technology design rules. Skills required include CMOS circuit design, timing analysis and simulation using static timing analysis tools. Programming skills (tcl, Python, C++) are a significant advantage.Required Technical and Professional ExpertiseCMOS circuit design, timing analysis and simulation using static timing analysis tools.Preferred Technical and Professional ExpertiseProgramming skills (tcl, Python, C++) are a significant advantage.
Responsibilities + Skills
Education
In a world where technology never stands still, we understand that, dedication to our clients success, innovation that matters, and trust and personal responsibility in all our relationships, lives in what we do as IBMers as we strive to be the catalyst that makes the world work better.
Experience
