Job Description
Job Description:Synthesize the Verilog RTL and create models and compile them to emulators like Veloce/Palladium/Zebu and/or FPGA platformsDevelop all aspects of hardware emulator implementation, with emphasis on design partitioning, synthesis, place and route, timing analysis & run time performance.Drive debug failures on emulator using latest technologies. Work with designers and SW driver team for testplan and debug.Work with tool vendors and push the methodology to improve the area/performance of the synthesized FPGA RTL.Work on third-party IP integration and system-level debugging.System level RTL simulation & design verification.Support chip bring up and post silicon debug.
Responsibilities + Skills
PhD in Computer Engineering, Computer Science, Electrical Engineering, or related field.
Education
Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 2+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience.
Experience
